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M48Z59 M48Z59Y
64Kb (8K x 8) ZEROPOWER(R) SRAM
INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY MICROPROCESSOR POWER-ON RESET (Valid even during battery back-up mode) AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48Z59: 4.50V VPFD 4.75V - M48Z59Y: 4.20V VPFD 4.50V SELF-CONTAINED BATTERY in the CAPHAT DIP PACKAGE PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT(R) TOP (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY and CRYSTAL PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 8K x 8 SRAMs DESCRIPTION The M48Z59/59Y ZEROPOWER(R) RAM is an 8K x 8 non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution. Table 1. Signal Names
A0-A12 DQ0-DQ7 RST E1 E2 G W VCC VSS January 1998 Address Inputs Data Inputs / Outputs Power Fail Reset Ouput (Open Drain) Chip Enable 1 Chip Enable 2 Output Enable Write Enable Supply Voltage Ground 1/14
SNAPHAT (SH) Battery
28
28 1
1
PCDIP28 (PC) Battery CAPHAT
SOH28 (MH)
Figure 1. Logic Diagram
VCC
13 A0-A12
8 DQ0-DQ7
W E1 E2 G M48Z59 M48Z59Y RST
VSS
AI01179B
M48Z59, M48Z59Y
Figure 2A. DIP Pin Connections
RST A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 28 1 27 2 26 3 25 4 24 5 23 6 7 M48Z59 22 8 M48Z59Y 21 20 9 19 10 18 11 17 12 13 16 14 15
AI01180B
Figure 2B. SOIC Pin Connections
VCC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3
RST A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 28 27 2 26 3 25 4 24 5 23 6 22 7 M48Z59Y 21 8 20 9 19 10 18 11 17 12 16 13 15 14
AI01181B
VCC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TSLD
(2)
Parameter Ambient Operating Temperature Storage Temperature (VCC Off) Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation
Value 0 to 70 -40 to 85 260 -0.3 to 7 -0.3 to 7 20 1
Unit C C C V V mA W
VIO VCC IO PD
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3 volts are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 3. Operating Modes (1)
Mode Deselect Deselect Write Read Read Deselect Deselect VSO to VPFD (min) VSO
(2)
VCC
E1 VIH
E2 X VIL VIH VIH VIH X X
G X X X VIL VIH X X
W X X VIL VIH VIH X X
DQ0-DQ7 High Z High Z DIN DOUT High Z High Z High Z
Power Standby Standby Active Active Active CMOS Standby Battery Back-up Mode
4.75V to 5.5V or 4.5V to 5.5V
X VIL VIL VIL X X
Notes: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 2. See Table 7 for details.
2/14
M48Z59, M48Z59Y
Figure 3. Block Diagram
A0-A12
DQ0-DQ7 LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY POWER 8K x 8 SRAM ARRAY E1 VPFD E2 W G
VCC
RST
VSS
AI01169B
DESCRIPTION (cont'd) The M48Z59/59Y is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 28 pin 600mil DIP CAPHATTM houses the M48Z59/59Y silicon with a long life lithium button cell in a single package. The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form.
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
Note that Output Hi-Z is defined as the point where data is no longer driven.
Figure 4. AC Testing Load Circuit
5V
1.9k DEVICE UNDER TEST 1k
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
AI01030
3/14
M48Z59, M48Z59Y
Table 5. Capacitance (1, 2) (TA = 25 C)
Symbol CIN CIO (3) Parameter Input Capacitance Input / Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 10 10 Unit pF pF
Notes: 1. Effective capacitance measured with power supply at 5V. 2. Sampled only, not 100% tested. 3. Outputs deselected.
Table 6. DC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol ILI (1) ILO
(1)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage (RST)
(2)
Test Condition 0V VIN VCC 0V VOUT VCC Outputs open E1 = VIH, E2 = VIL E1 = VCC - 0.2V, E2 = VSS + 0.2V
Min
Max 1 5 50 3 3
Unit A A mA mA mA V V V V V
ICC ICC1 ICC2 VIL VIH VOL VOH
-0.3 2.2 IOL = 2.1mA IOL = 10mA IOH = -1mA 2.4
0.8 VCC + 0.3 0.4 0.4
Output High Voltage
Notes: 1. Outputs Deselected. 2. The RST pin is Open Drain.
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70C)
Symbol VPFD VPFD VSO tDR
(2)
Parameter Power-fail Deselect Voltage (M48Z59/59Y) Power-fail Deselect Voltage (M48Z59/59YY) Battery Back-up Switchover Voltage Expected Data Retention Time
Min 4.5 4.2
Typ 4.6 4.35 3.0
Max 4.75 4.5
Unit V V V YEARS
10
Notes: 1. All voltages referenced to VSS. 2. At 25 C.
DESCRIPTION (cont'd) For the 28 lead SOIC, the battery package (i.e. SNAPHAT) part number is "M4Z28-BR00SH1". A power-on reset output provides a reset pulse to the microprocessor. The reset pulls low (open drain) an power-down and remains low on powerup for 40ms to 200ms after VCC passes VPFD. The M48Z59/59Y also has its own Power-fail Detect
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circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data until valid power returns.
M48Z59, M48Z59Y
Table 8. Power Down/Up Mode AC Characteristics (TA = 0 to 70C)
Symbol tPD tF (1) tFB
(2)
Parameter E1 or W at VIH or E2 at VIL before Power Down VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSO VCC Fall Time VPFD(min) to VPFD (max) VCC Rise Time VSO to VPFD (min) VCC Rise Time VPFD(max) to RST High
Min 0 300 10 10 1 40
Max
Unit s s s s s
tR tRB tREC
200
ms
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 5. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tPD tFB tDR tRB tREC RST tR
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01384C
READ MODE The M48Z59/59Y is in the Read Mode whenever W (Write Enable) is high, E1 (Chip Enable 1) is low, and E2 (Chip Enable 2) is high. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E1, E2, and G access times are also satisfied. If the E1, E2 and G access times are not met, valid data will be available after
the latter of the Chip Enable Access times (tE1LQV or tE2HQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E1, E2 and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E1, E2 and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
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M48Z59, M48Z59Y
Table 9. Read Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z59 / M48Z59Y Symbol Parameter Min tAVAV tAVQV (1) tE1LQV tE2HQV tGLQV tE1LQX tE2HQX tGLQX tE1HQZ
(1) (1) (1) (2) (2) (2) (2)
-70 Max
Unit
Read Cycle Time Address Valid to Output Valid Chip Enable 1 Low to Output Valid Chip Enable 2 High to Output Valid Output Enable Low to Output Valid Chip Enable 1 Low to Output Transition Chip Enable 2 High to Output Transition Output Enable Low to Output Transition Chip Enable 1 High to Output Hi-Z Chip Enable 2 Low to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
70 70 70 70 35 5 5 5 25 25 25 10
ns ns ns ns ns ns ns ns ns ns ns ns
tE2LQZ (2) tGHQZ
(2)
tAXQX (1)
Notes: 1. CL = 100pF (see Figure 4). 2. CL = 5pF (see Figure 4).
Figure 6. Read Mode AC Waveforms
tAVAV A0-A12 tAVQV tE1LQV E1 tE1LQX tE2HQV E2 tE2HQX tGLQV G tGLQX DQ0-DQ7 VALID
AI00962
VALID tAXQX tE1HQZ
tE2LQZ
tGHQZ
Note: Write Enable (W) = High.
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M48Z59, M48Z59Y
Table 10. Write Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z59 / M48Z59Y Symbol Parameter Min tAVAV tAVWL tAVE1L tAVE2H tWLWH tE1LE1H tE2HE2L tWHAX tE1HAX tE2LAX tDVWH tDVE1H tDVE2L tWHDX tE1HDX tE2LDX tWLQZ (1, 2) tAVWH tAVE1H tAVE2L tWHQX
(1, 2)
-70 Max
Unit
Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable 1 Low Address Valid to Chip Enable 2 High Write Enable Pulse Width Chip Enable 1 Low to Chip Enable 1 High Chip Enable 2 High to Chip Enable 2 Low Write Enable High to Address Transition Chip Enable 1 High to Address Transition Chip Enable 2 Low to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable 1 High Input Valid to Chip Enable 2 Low Write Enable High to Input Transition Chip Enable 1 High to Input Transition Chip Enable 2 Low to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable 1 High Address Valid to Chip Enable 2 Low Write Enable High to Output Transition
70 0 0 0 50 55 55 0 0 0 30 30 30 5 5 5 25 60 60 60 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. CL = 5pF (see Figure 4). 2. If E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state.
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M48Z59, M48Z59Y
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A12 VALID tAVWH tAVE1L E1 tAVE2H E2 tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI00963
tWHAX
tWHQX
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A12 VALID tAVE1H tAVE1L E1 tE1LE1H tE1HAX
tAVE2L tAVE2H E2 tAVWL W tE1HDX tE2LDX DQ0-DQ7 DATA INPUT tDVE1H tDVE2L tE2HE2L tE2LAX
AI00964B
8/14
M48Z59, M48Z59Y
WRITE MODE The M48Z59/59Y is in the Write Mode whenever W and E1 are low and E2 is high. The start of a write is referenced from the latter occurring falling edge of W or E1, or the rising edge of E2. A write is terminated by the earlier rising edge of W or E1, or the falling edge of E2. The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low for a minimum of tE1HAX or tE2LAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E1 and G and a high on E2, a low on W will disable the outputs tWLQZ after W falls. DATA RETENTION MODE With valid VCC applied, the M48Z59/59Y operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD(max), VPFD(min) window. All outputs become high impedance, and all inputs are treated as "don't care." Note: A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z59/59Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data. The internal button cell will maintain data in the M48Z59/59Y for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues for tREC until VCC reaches VPFD(min). E1 should be kept high or E2 low as VCC rises past VPFD(min) to prevent inadvertent write cycles prior to system stabilization. Normal RAM operation can resume tREC after VCC exceeds VPFD(max). For more information on Battery Storage Life refer to the Application Note AN1012. POWER-ON RESET The M48Z59/59Y continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for 40ms to 200ms after VCC passes VPFD. A 1k resistor is recommended in order to control the rise-time. The reset pulse remains active with VCC at VSS. POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 9) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommeded to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 9. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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M48Z59, M48Z59Y
ORDERING INFORMATION SCHEME
Example:
M48Z59Y
-70 MH
1
TR
Supply Voltage and Write Protect Voltage 59 (1) VCC = 4.75V to 5.5V VPFD = 4.5V to 4.75V 59Y VCC = 4.5V to 5.5V VPFD = 4.2V to 4.5V -70
Speed 70ns PC MH
Package PCDIP28
(2)
Temp. Range 1 0 to 70 C
Shipping Method for SOIC blank Tubes TR Tape & Reel
SOH28
Notes: 1. The M48Z59 part is offered with the PCDIP28 (i.e. CAPHAT) package only. 2. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number "M4Z28-BR00SH1" in plastic tube or "M4Z28-BR00SH1TR" in Tape & Reel form. Caution: Do not place the SNAPHAT battery package "M4Z28-BR00SH1" in conductive foam since this will drain the lithium button-cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you.
10/14
M48Z59, M48Z59Y
PCDIP28 - 28 pin Plastic DIP, battery CAPHAT
Symb Typ A A1 A2 B B1 C D E e1 e3 eA L N
PCDIP28
mm Min 8.89 0.38 8.38 0.38 1.14 0.20 39.37 17.83 2.29 29.72 15.24 3.05 28 Max 9.65 0.76 8.89 0.53 1.78 0.31 39.88 18.34 2.79 36.32 16.00 3.81 Typ
inches Min 0.350 0.015 0.330 0.015 0.045 0.008 1.550 0.702 0.090 1.170 0.600 0.120 28 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.570 0.722 0.110 1.430 0.630 0.150
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Drawing is not to scale.
11/14
M48Z59, M48Z59Y
SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT
Symb Typ A A1 A2 B C D E e eB H L N CP
SOH28
mm Min Max 3.05 0.05 2.34 0.36 0.15 17.71 8.23 1.27 - 3.20 11.51 0.41 0 28 0.10 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 Typ
inches Min Max 0.120 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH
Drawing is not to scale.
12/14
M48Z59, M48Z59Y
SH - SNAPHAT Housing for 28 lead Plastic Small Outline
Symb Typ A A1 A2 A3 B D E eA eB L
SH28
mm Min Max 9.78 6.73 6.48 7.24 6.99 0.38 0.46 21.21 14.22 15.55 3.20 2.03 0.56 21.84 14.99 15.95 3.61 2.29 Typ
inches Min Max 0.385 0.265 0.255 0.285 0.275 0.015 0.018 0.835 0.560 0.612 0.126 0.080 0.022 0.860 0.590 0.628 0.142 0.090
A1
A2 A A3
eA D
B eB
L
E
SH
Drawing is not to scale.
13/14
M48Z59, M48Z59Y
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1998 SGS-THOMSON Microelectronics - All Rights Reserved (R) ZEROPOWER and SNAPHAT are registered trademarks of SGS-THOMSON Microelectronics TM CAPHAT and BYTEWIDE are trademarks of SGS-THOMSON Microelectronics SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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